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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:33:02 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | 0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c (patch) | |
| tree | b28564457fa1f56fa01d5fe719adf144e9ac3475 /bsd-user | |
| parent | 67d74e4c54236b53917edfa9f52efb4207064014 (diff) | |
| download | qemu-0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c.zip qemu-0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c.tar.gz qemu-0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c.tar.bz2 | |
hw/intc/arm_gicv3: Add irq non-maskable property
A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
non-maskable property in PendingIrq and GICR/GICD. Since add new device
state, it also needs to be migrated, so also save NMI info in
vmstate_gicv3_cpu and vmstate_gicv3.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'bsd-user')
0 files changed, 0 insertions, 0 deletions