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authorNicholas Piggin <npiggin@gmail.com>2021-05-01 17:24:35 +1000
committerDavid Gibson <david@gibson.dropbear.id.au>2021-05-04 13:12:46 +1000
commit526cdce771fa27c37b68fd235ff9f1caa0bdd563 (patch)
tree17ecd66691cbeb0e317e767001362a637200a3d0 /block/vmdk.c
parent8b7e6b07a46809a75b857d30ae47e697e0f9b724 (diff)
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target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=0b10 mode. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210501072436.145444-3-npiggin@gmail.com> [dwg: Corrected tab indenting] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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