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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-22 23:05:01 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-05 13:44:07 -0800 |
| commit | 0953674ed0acacfa9b2409678f8ce8333398ee1c (patch) | |
| tree | 5b84b8ee0c68499cbb51a7b05f9f12911df6d99a /accel/tcg | |
| parent | 20f7fe93f59fd840b06de2341f789725e382902b (diff) | |
| download | qemu-0953674ed0acacfa9b2409678f8ce8333398ee1c.zip qemu-0953674ed0acacfa9b2409678f8ce8333398ee1c.tar.gz qemu-0953674ed0acacfa9b2409678f8ce8333398ee1c.tar.bz2 | |
accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup
Using an atomic write or read-write insn on ROM is basically
a happens-never case. Handle it via stop-the-world, which
will generate non-atomic serial code, where we can correctly
ignore the write while producing the correct read result.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg')
| -rw-r--r-- | accel/tcg/cputlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index deafcc7..b49fb0d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1831,7 +1831,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } /* Notice an IO access or a needs-MMU-lookup access */ - if (unlikely(tlb_addr & TLB_MMIO)) { + if (unlikely(tlb_addr & (TLB_MMIO | TLB_DISCARD_WRITE))) { /* There's really nothing that can be done to support this apart from stop-the-world. */ goto stop_the_world; |