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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-08-22 01:30:51 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2023-09-06 11:19:33 +0200 |
| commit | 718209358f2e4f231cbacf974c3299c4fe7beb83 (patch) | |
| tree | 24d2e1781edb967f496cae2088085950b067bf40 /accel/accel-user.c | |
| parent | 761a13b239468c1dd175c2d93fc09c1693a937e7 (diff) | |
| download | qemu-718209358f2e4f231cbacf974c3299c4fe7beb83.zip qemu-718209358f2e4f231cbacf974c3299c4fe7beb83.tar.gz qemu-718209358f2e4f231cbacf974c3299c4fe7beb83.tar.bz2 | |
target/ppc: Fix LQ, STQ register-pair order for big-endian
LQ, STQ have the same register-pair ordering as LQARX/STQARX., which is
the even (lower) register contains the most significant bits. This is
not implemented correctly for big-endian.
do_ldst_quad() has variables low_addr_gpr and high_addr_gpr which is
confusing because they are low and high addresses, whereas LQARX/STQARX.
and most such things use the low and high values for lo/hi variables.
The conversion to native 128-bit memory access functions missed this
strangeness.
Fix this by changing the if condition, and change the variable names to
hi/lo to match convention.
Cc: qemu-stable@nongnu.org
Reported-by: Ivan Warren <ivan@vmfacility.fr>
Fixes: 57b38ffd0c6f ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1836
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'accel/accel-user.c')
0 files changed, 0 insertions, 0 deletions