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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-01-30 18:24:58 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-03 12:59:24 +0000 |
| commit | 1748ef03c562dd4e5222e6d665142b25c0cfb1d1 (patch) | |
| tree | 35814fdaa84fa80fec1c311f29f2cb5037f3a506 /accel/accel-softmmu.h | |
| parent | 34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54 (diff) | |
| download | qemu-1748ef03c562dd4e5222e6d665142b25c0cfb1d1.zip qemu-1748ef03c562dd4e5222e6d665142b25c0cfb1d1.tar.gz qemu-1748ef03c562dd4e5222e6d665142b25c0cfb1d1.tar.bz2 | |
target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents). This trapping is independent of whether
fine-grained traps are enabled or not.
Implement these extra traps. (We don't implement DBGDTR_EL0,
DBGDTRRX_EL0 and DBGDTRTX_EL0.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
Diffstat (limited to 'accel/accel-softmmu.h')
0 files changed, 0 insertions, 0 deletions