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authorPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>2012-03-05 14:39:13 +1000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2012-03-07 02:20:19 +0100
commite32605062cd62c2a958ad28a6ad7de4eeab12027 (patch)
tree4b6b2d984fa6082a0c29333edd3080f2f11aa534 /Makefile.target
parente9f186e514a70557d695cadd2c2287ef97737023 (diff)
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xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific system level control register (SLCR) module. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'Makefile.target')
-rw-r--r--Makefile.target1
1 files changed, 1 insertions, 0 deletions
diff --git a/Makefile.target b/Makefile.target
index 4dd415c..5f3fc40 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -349,6 +349,7 @@ obj-arm-y += versatile_pci.o
obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
+obj-arm-y += xilinx_zynq.o zynq_slcr.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o