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| author | Thomas Huth <thuth@redhat.com> | 2023-09-29 14:37:27 +0200 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-10-12 00:37:39 +0300 |
| commit | 5d0ce90dd6881b044bf1a28dc966eee44bcc1dde (patch) | |
| tree | 61e7f1c3d176c925d1921138a4eba7b2c347c334 /MAINTAINERS | |
| parent | 740ee84db8732c11e2db8bba6630046634f3c5e9 (diff) | |
| download | qemu-5d0ce90dd6881b044bf1a28dc966eee44bcc1dde.zip qemu-5d0ce90dd6881b044bf1a28dc966eee44bcc1dde.tar.gz qemu-5d0ce90dd6881b044bf1a28dc966eee44bcc1dde.tar.bz2 | |
MAINTAINERS: Add unowned RISC-V related files to the right sections
There are a bunch of RISC-V files that are currently not covered
by the "get_maintainers.pl" script. Add them to the right sections
in MAINTAINERS to fix this problem.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 93756ec..e80fca8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -318,8 +318,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> L: qemu-riscv@nongnu.org S: Supported +F: configs/targets/riscv* +F: docs/system/target-riscv.rst F: target/riscv/ F: hw/riscv/ +F: hw/intc/riscv* F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ @@ -331,6 +334,7 @@ L: qemu-riscv@nongnu.org S: Supported F: target/riscv/insn_trans/trans_xthead.c.inc F: target/riscv/xthead*.decode +F: disas/riscv-xthead* RISC-V XVentanaCondOps extension M: Philipp Tomsich <philipp.tomsich@vrull.eu> @@ -338,6 +342,7 @@ L: qemu-riscv@nongnu.org S: Maintained F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc +F: disas/riscv-xventana* RENESAS RX CPUs R: Yoshinori Sato <ysato@users.sourceforge.jp> @@ -1527,6 +1532,7 @@ Microchip PolarFire SoC Icicle Kit M: Bin Meng <bin.meng@windriver.com> L: qemu-riscv@nongnu.org S: Supported +F: docs/system/riscv/microchip-icicle-kit.rst F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c F: hw/misc/mchp_pfsoc_dmc.c @@ -1542,6 +1548,7 @@ Shakti C class SoC M: Vijai Kumar K <vijai@behindbytes.com> L: qemu-riscv@nongnu.org S: Supported +F: docs/system/riscv/shakti-c.rst F: hw/riscv/shakti_c.c F: hw/char/shakti_uart.c F: include/hw/riscv/shakti_c.h @@ -1553,6 +1560,7 @@ M: Bin Meng <bin.meng@windriver.com> M: Palmer Dabbelt <palmer@dabbelt.com> L: qemu-riscv@nongnu.org S: Supported +F: docs/system/riscv/sifive_u.rst F: hw/*/*sifive*.c F: include/hw/*/*sifive*.h @@ -3573,7 +3581,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com> L: qemu-riscv@nongnu.org S: Maintained F: tcg/riscv/ -F: disas/riscv.c +F: disas/riscv.[ch] S390 TCG target M: Richard Henderson <richard.henderson@linaro.org> |