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| author | Atish Patra <atishp@rivosinc.com> | 2025-01-10 00:21:39 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | fdb7bce43f9008d83e1edfd260a8165119b61ca5 (patch) | |
| tree | b2a2834543032758feb5ce7ffb1d59221beb0703 | |
| parent | 2a754d6957e70889e7208f4d2d6bdb9714508c9b (diff) | |
| download | qemu-fdb7bce43f9008d83e1edfd260a8165119b61ca5.zip qemu-fdb7bce43f9008d83e1edfd260a8165119b61ca5.tar.gz qemu-fdb7bce43f9008d83e1edfd260a8165119b61ca5.tar.bz2 | |
target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-11-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 671fc3d..fe470f6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1587,6 +1587,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), + MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), + MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), + MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), + MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), |