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| author | Peter Maydell <peter.maydell@linaro.org> | 2011-04-11 16:26:21 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-04-12 23:33:33 +0200 |
| commit | fc2a9b37849d25d21d161c1319581420499ab4b2 (patch) | |
| tree | 350c76f339820c4c026c996254adf768cdf00be6 | |
| parent | 600b828c448f108b89e1f864f0420a49ccb70d43 (diff) | |
| download | qemu-fc2a9b37849d25d21d161c1319581420499ab4b2.zip qemu-fc2a9b37849d25d21d161c1319581420499ab4b2.tar.gz qemu-fc2a9b37849d25d21d161c1319581420499ab4b2.tar.bz2 | |
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms:
* all instructions except VMOVN,VQMOVN must UNDEF
if Q==1 && (Vd<0> == 1 || Vm<0> == 1)
* VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q == 1 || Vm<0> == 1
* VSHLL,VCVT.F32.F16 UNDEF if Q == 1 || Vd<0> == 1
(The only other UNDEF case is VZIP,VUZP if Q == 0 && size == 10,
which we already handle.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-arm/translate.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 4728248..b647c7b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5677,6 +5677,10 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) if ((neon_2rm_sizes[op] & (1 << size)) == 0) { return 1; } + if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) && + q && ((rm | rd) & 1)) { + return 1; + } switch (op) { case NEON_2RM_VREV64: for (pass = 0; pass < (q ? 2 : 1); pass++) { @@ -5747,6 +5751,9 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) break; case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: /* also VQMOVUN; op field and mnemonics don't line up */ + if (rm & 1) { + return 1; + } TCGV_UNUSED(tmp2); for (pass = 0; pass < 2; pass++) { neon_load_reg64(cpu_V0, rm + pass); @@ -5762,7 +5769,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } break; case NEON_2RM_VSHLL: - if (q) { + if (q || (rd & 1)) { return 1; } tmp = neon_load_reg(rm, 0); @@ -5776,8 +5783,10 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } break; case NEON_2RM_VCVT_F16_F32: - if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) - return 1; + if (!arm_feature(env, ARM_FEATURE_VFP_FP16) || + q || (rm & 1)) { + return 1; + } tmp = tcg_temp_new_i32(); tmp2 = tcg_temp_new_i32(); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); @@ -5798,8 +5807,10 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp); break; case NEON_2RM_VCVT_F32_F16: - if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) - return 1; + if (!arm_feature(env, ARM_FEATURE_VFP_FP16) || + q || (rd & 1)) { + return 1; + } tmp3 = tcg_temp_new_i32(); tmp = neon_load_reg(rm, 0); tmp2 = neon_load_reg(rm, 1); |