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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-04-02 09:54:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-02 09:54:41 +0100 |
| commit | fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876 (patch) | |
| tree | 316106edb6d81e9656e626eca7c94a7b8b48bbb2 | |
| parent | 6af9d12c88b9720f209912f6e4b01fefe5906d59 (diff) | |
| download | qemu-fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876.zip qemu-fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876.tar.gz qemu-fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876.tar.bz2 | |
target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and
EL0 accesses to cp15 registers. We incorrectly implemented this so
they trap to EL1 when we detect the need for a HSTR trap at code
generation time. (The check in access_check_cp_reg() which we do at
runtime to catch traps from EL0 is correctly routing them to EL2.)
Use the correct target EL when generating the code to take the trap.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226
Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c8a2470..69585e6 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4585,7 +4585,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_gen_andi_i32(t, t, 1u << maskbit); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); - gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); /* * gen_exception_insn() will set is_jmp to DISAS_NORETURN, * but since we're conditionally branching over it, we want |