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author | Peter Maydell <peter.maydell@linaro.org> | 2024-04-08 16:24:21 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-08 16:24:21 +0100 |
commit | fa706e013dc0ad9cfcf6e69f42806c321afdbae2 (patch) | |
tree | a2f2c18c8b9a9b8c8c959bf4690473b7dce6da9d | |
parent | d276a51d1835d40fb19733f394f5de32cd89b5be (diff) | |
parent | 19b254e86a900dc5ee332e3ac0baf9c521301abf (diff) | |
download | qemu-fa706e013dc0ad9cfcf6e69f42806c321afdbae2.zip qemu-fa706e013dc0ad9cfcf6e69f42806c321afdbae2.tar.gz qemu-fa706e013dc0ad9cfcf6e69f42806c321afdbae2.tar.bz2 |
Merge tag 'pull-target-arm-20240408' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm:
* Use correct SecuritySpace for AArch64 AT ops at EL3
* Fix CNTPOFF_EL2 trap to missing EL3
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# gpg: Signature made Mon 08 Apr 2024 16:21:05 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240408' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3
target/arm: Fix CNTPOFF_EL2 trap to missing EL3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/arm/helper.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f3a5b5..a620481 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3452,7 +3452,8 @@ static CPAccessResult gt_cntpoff_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) { + if (arm_current_el(env) == 2 && arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ECVEN)) { return CP_ACCESS_TRAP_EL3; } return CP_ACCESS_OK; @@ -3878,6 +3879,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, ARMMMUIdx mmu_idx; uint64_t hcr_el2 = arm_hcr_el2_eff(env); bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); + bool for_el3 = false; + ARMSecuritySpace ss; switch (ri->opc2 & 6) { case 0: @@ -3895,6 +3898,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; + for_el3 = true; break; default: g_assert_not_reached(); @@ -3913,8 +3917,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, g_assert_not_reached(); } - env->cp15.par_el[1] = do_ats_write(env, value, access_type, - mmu_idx, arm_security_space(env)); + ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env); + env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); |