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| author | Alex Bennée <alex.bennee@linaro.org> | 2023-11-06 18:50:54 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2023-11-08 15:15:23 +0000 |
| commit | f654387b8138ccbc5d9e3eeb6fedd2b73fbfe4b4 (patch) | |
| tree | 85deb6da480b2674731ccbc62cafd91b5685918d | |
| parent | 8ce4d441cb1e9a1c30afb762f0f3b1faac53bb6d (diff) | |
| download | qemu-f654387b8138ccbc5d9e3eeb6fedd2b73fbfe4b4.zip qemu-f654387b8138ccbc5d9e3eeb6fedd2b73fbfe4b4.tar.gz qemu-f654387b8138ccbc5d9e3eeb6fedd2b73fbfe4b4.tar.bz2 | |
target/arm: hide all versions of DBGD[RS]AR from gdbstub
This avoids two duplicates being presented to gdbstub. As the
registers are RAZ anyway it is unlikely their value would be of use to
someone using gdbstub anyway.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231106185112.2755262-5-alex.bennee@linaro.org>
| -rw-r--r-- | target/arm/debug_helper.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 79a3659..cbfba53 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -937,14 +937,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { */ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tdra, - .type = ARM_CP_CONST, .resetvalue = 0 }, + .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 }, { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, .access = PL1_R, .accessfn = access_tdra, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tdra, - .type = ARM_CP_CONST, .resetvalue = 0 }, + .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 }, /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, @@ -1065,9 +1065,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { /* 64 bit access versions of the (dummy) debug registers */ { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO_GDB, + .resetvalue = 0 }, { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO_GDB, + .resetvalue = 0 }, }; static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, |