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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-04-06 22:26:21 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-04-13 12:07:00 +0200
commitf4349ba966abfe39f5d98694abd7c7551d5c8c02 (patch)
tree8ff25b143ea99323701d3b28f8fb4c15bd043f30
parent62271205bcfaee440d06c06060ee79dac657caff (diff)
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target/mips: Fix TCG temporary leak in gen_cache_operation()
Fix a TCG temporary leak when translating CACHE opcode. Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
-rw-r--r--target/mips/translate.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3..71fa5ec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(t0);
}
#if defined(TARGET_MIPS64)