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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-13 23:05:02 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:35 +0200 |
| commit | f3185ec2f35e43c06384f5ac5edc4edfbfd11623 (patch) | |
| tree | 7f2f49d920cc32ed59baee3c6acac15f07ee92f7 | |
| parent | 920b48cc14fe44a466f7387263993e86b4e21bce (diff) | |
| download | qemu-f3185ec2f35e43c06384f5ac5edc4edfbfd11623.zip qemu-f3185ec2f35e43c06384f5ac5edc4edfbfd11623.tar.gz qemu-f3185ec2f35e43c06384f5ac5edc4edfbfd11623.tar.bz2 | |
target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-23-f4bug@amsat.org>
| -rw-r--r-- | target/mips/internal.h | 6 | ||||
| -rw-r--r-- | target/mips/tcg/sysemu/tlb_helper.c | 13 |
2 files changed, 7 insertions, 12 deletions
diff --git a/target/mips/internal.h b/target/mips/internal.h index 558cdca..c175170 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,12 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index bf242f5..a45146a 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -26,8 +26,8 @@ #include "hw/mips/cpudevs.h" /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, } /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <= (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, } /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID = env->CP0_MemoryMapID; |