diff options
| author | Atish Patra <atishp@rivosinc.com> | 2025-01-10 00:21:33 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | f2548886b3dff228b82e91808553616c4b8d14a8 (patch) | |
| tree | 836cbe1b2f51de491ab06d17fb2b9f175d215f00 | |
| parent | 5e33a20827150345350bede07e26a1bae320e682 (diff) | |
| download | qemu-f2548886b3dff228b82e91808553616c4b8d14a8.zip qemu-f2548886b3dff228b82e91808553616c4b8d14a8.tar.gz qemu-f2548886b3dff228b82e91808553616c4b8d14a8.tar.bz2 | |
target/riscv: Add properties for counter delegation ISA extensions
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-5-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_cfg.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f5772a..da40f68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), @@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 4fe2144..561f511 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,8 @@ struct RISCVCPUConfig { bool ext_ztso; bool ext_smstateen; bool ext_sstc; + bool ext_smcdeleg; + bool ext_ssccfg; bool ext_smcntrpmf; bool ext_smcsrind; bool ext_sscsrind; |