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author | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-25 10:03:22 +0200 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-25 13:27:54 +0200 |
commit | f0f0136abba688a6516647a79cc91e03fad6d5d7 (patch) | |
tree | 1e33d58e6c6317ef9718914aef68e5586171f352 | |
parent | 8225bff7c5db504f50e54ef66b079854635dba70 (diff) | |
download | qemu-f0f0136abba688a6516647a79cc91e03fad6d5d7.zip qemu-f0f0136abba688a6516647a79cc91e03fad6d5d7.tar.gz qemu-f0f0136abba688a6516647a79cc91e03fad6d5d7.tar.bz2 |
target/i386: no single-step exception after MOV or POP SS
Intel SDM 18.3.1.4 "If an occurrence of the MOV or POP instruction
loads the SS register executes with EFLAGS.TF = 1, no single-step debug
exception occurs following the MOV or POP instruction."
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r-- | target/i386/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ebcff87..9782250 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2273,7 +2273,7 @@ gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) if (recheck_tf) { gen_helper_rechecking_single_step(tcg_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->flags & HF_TF_MASK) { + } else if ((s->flags & HF_TF_MASK) && !inhibit) { gen_helper_single_step(tcg_env); } else if (jr && /* give irqs a chance to happen */ |