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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-03-30 10:13:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | f06193c40b90932b4b6fabb5a038c26c35f86769 (patch) | |
| tree | 475414f4543da2bf8f47a0609e8cb2595aecae8e | |
| parent | a775398be2e9ee2f2158dbdd0938593e3d002f62 (diff) | |
| download | qemu-f06193c40b90932b4b6fabb5a038c26c35f86769.zip qemu-f06193c40b90932b4b6fabb5a038c26c35f86769.tar.gz qemu-f06193c40b90932b4b6fabb5a038c26c35f86769.tar.bz2 | |
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/vector_helper.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 99f3134..576b14e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) /* Vector Whole Register Move */ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) { - /* EEW = 8 */ + /* EEW = SEW */ uint32_t maxsz = simd_maxsz(desc); - uint32_t i = env->vstart; + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t startb = env->vstart * sewb; + uint32_t i = startb; memcpy((uint8_t *)vd + H1(i), (uint8_t *)vs2 + H1(i), - maxsz - env->vstart); + maxsz - startb); env->vstart = 0; } |