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| author | Igor Mammedov <imammedo@redhat.com> | 2022-05-24 11:10:19 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-06-06 09:26:54 +0200 |
| commit | efb3934adf9ee7794db7e0ade9f576c634592891 (patch) | |
| tree | bf405f6f8aa8ac1f621501d382b81bbb0208cb3c | |
| parent | d426ff938b3f95e0b04bb410d47ae50359340a16 (diff) | |
| download | qemu-efb3934adf9ee7794db7e0ade9f576c634592891.zip qemu-efb3934adf9ee7794db7e0ade9f576c634592891.tar.gz qemu-efb3934adf9ee7794db7e0ade9f576c634592891.tar.bz2 | |
x86: cpu: make sure number of addressable IDs for processor cores meets the spec
Accourding Intel's CPUID[EAX=04H] resulting bits 31 - 26 in EAX
should be:
"
**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique
Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of
bits of the initial APIC ID.
"
ensure that values stored in EAX[31-26] always meets this condition.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220524151020.2541698-2-imammedo@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9fdfec9..94cc4a8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5287,7 +5287,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ *eax &= ~0xFC000000; if ((*eax & 31) && cs->nr_cores > 1) { - *eax |= (cs->nr_cores - 1) << 26; + *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax = *ebx = *ecx = *edx = 0; |