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| author | Cédric Le Goater <clg@kaod.org> | 2024-07-17 08:30:18 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-07-21 07:46:38 +0200 |
| commit | eea55625df839813c66c5e2e8f41d9131d591f6c (patch) | |
| tree | 408671ed4603349d3825d33f959ed2c31515b738 | |
| parent | cc8bae6f6270c52c8f9854a83f9cefec3e5ec108 (diff) | |
| download | qemu-eea55625df839813c66c5e2e8f41d9131d591f6c.zip qemu-eea55625df839813c66c5e2e8f41d9131d591f6c.tar.gz qemu-eea55625df839813c66c5e2e8f41d9131d591f6c.tar.bz2 | |
aspeed: Introduce a AspeedSoCClass 'boot_from_emmc' handler
Report support on the AST2600 SoC if the boot-from-eMMC HW strapping
bit is set at the board level. AST2700 also has support but it is not
yet ready in QEMU and others SoCs do not have support, so return false
always for these.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 8 | ||||
| -rw-r--r-- | hw/arm/aspeed_soc_common.c | 7 | ||||
| -rw-r--r-- | include/hw/arm/aspeed_soc.h | 1 |
3 files changed, 16 insertions, 0 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 31713de..be3eb70 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -646,6 +646,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) } } +static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) +{ + uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), + "hw-strap1", &error_abort); + return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); +} + static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { static const char * const valid_cpu_types[] = { @@ -673,6 +680,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) sc->memmap = aspeed_soc_ast2600_memmap; sc->num_cpus = 2; sc->get_irq = aspeed_soc_ast2600_get_irq; + sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; } static const TypeInfo aspeed_soc_ast2600_types[] = { diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 1e8f255..0555146 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -134,6 +134,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) } } +static bool aspeed_soc_boot_from_emmc(AspeedSoCState *s) +{ + return false; +} + static Property aspeed_soc_properties[] = { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), @@ -145,9 +150,11 @@ static Property aspeed_soc_properties[] = { static void aspeed_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); dc->realize = aspeed_soc_realize; device_class_set_props(dc, aspeed_soc_properties); + sc->boot_from_emmc = aspeed_soc_boot_from_emmc; } static const TypeInfo aspeed_soc_types[] = { diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 849ba37..624d489 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -164,6 +164,7 @@ struct AspeedSoCClass { const hwaddr *memmap; uint32_t num_cpus; qemu_irq (*get_irq)(AspeedSoCState *s, int dev); + bool (*boot_from_emmc)(AspeedSoCState *s); }; const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); |