diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
commit | ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 (patch) | |
tree | 56930bb977234b0836ed9e57fba0622a1facd3d3 | |
parent | 1bc04a8880374407c4b12d82ceb8752e12ff5336 (diff) | |
download | qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.zip qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.tar.gz qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.tar.bz2 |
target/arm: Make MPU_CTRL register banked for v8M
Make the MPU_CTRL register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
-rw-r--r-- | hw/intc/armv7m_nvic.c | 9 | ||||
-rw-r--r-- | target/arm/cpu.h | 2 | ||||
-rw-r--r-- | target/arm/helper.c | 5 | ||||
-rw-r--r-- | target/arm/machine.c | 3 |
4 files changed, 11 insertions, 8 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c3c214c..a4c298f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return cpu->pmsav7_dregion << 8; break; case 0xd94: /* MPU_CTRL */ - return cpu->env.v7m.mpu_ctrl; + return cpu->env.v7m.mpu_ctrl[attrs.secure]; case 0xd98: /* MPU_RNR */ return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ @@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " "UNPREDICTABLE\n"); } - cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | - R_V7M_MPU_CTRL_HFNMIENA_MASK | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); + cpu->env.v7m.mpu_ctrl[attrs.secure] + = value & (R_V7M_MPU_CTRL_ENABLE_MASK | + R_V7M_MPU_CTRL_HFNMIENA_MASK | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); tlb_flush(CPU(cpu)); break; case 0xd98: /* MPU_RNR */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 425adc3..29ffb26 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -429,7 +429,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl; /* MPU_CTRL */ + unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; uint32_t primask[2]; uint32_t faultmask[2]; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4db191e..cc68688 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7091,7 +7091,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl & + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -8251,7 +8251,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 7f894e5..666655d8 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), - VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() }, @@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security = { 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; |