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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:43 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:36 +0000 |
| commit | ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c (patch) | |
| tree | feba9c0c20b63da946fce02b844711b89d55d52a | |
| parent | 691f1ffdfc446acc1a9f0831fcced5012f6de52a (diff) | |
| download | qemu-ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c.zip qemu-ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c.tar.gz qemu-ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c.tar.bz2 | |
target/arm: Fault on invalid TCR_ELx.TxSZ
Without FEAT_LVA, the behaviour of programming an invalid value
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
minimum value requires a Translation fault.
It is most self-consistent to choose to generate the fault always.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 32 | ||||
| -rw-r--r-- | target/arm/internals.h | 1 |
2 files changed, 29 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bf50fd..dd4d95b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11190,8 +11190,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, max_tsz; + bool epd, hpd, using16k, using64k, tsz_oob; + int select, tsz, tbi, max_tsz, min_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -11232,9 +11232,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } else { max_tsz = 39; } + min_tsz = 16; /* TODO: ARMv8.2-LVA */ - tsz = MIN(tsz, max_tsz); - tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + if (tsz > max_tsz) { + tsz = max_tsz; + tsz_oob = true; + } else if (tsz < min_tsz) { + tsz = min_tsz; + tsz_oob = true; + } else { + tsz_oob = false; + } /* Present TBI as a composite with TBID. */ tbi = aa64_va_parameter_tbi(tcr, mmu_idx); @@ -11251,6 +11259,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .hpd = hpd, .using16k = using16k, .using64k = using64k, + .tsz_oob = tsz_oob, }; } @@ -11374,6 +11383,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; + + /* + * If TxSZ is programmed to a value larger than the maximum, + * or smaller than the effective minimum, it is IMPLEMENTATION + * DEFINED whether we behave as if the field were programmed + * within bounds, or if a level 0 Translation fault is generated. + * + * With FEAT_LVA, fault on less than minimum becomes required, + * so our choice is to always raise the fault. + */ + if (param.tsz_oob) { + fault_type = ARMFault_Translation; + goto do_fault; + } + addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748..ef6c25d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1055,6 +1055,7 @@ typedef struct ARMVAParameters { bool hpd : 1; bool using16k : 1; bool using64k : 1; + bool tsz_oob : 1; /* tsz has been clamped to legal range */ } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |