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| author | Alex Williamson <alex.williamson@redhat.com> | 2018-12-12 12:39:16 -0700 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2018-12-19 16:48:16 -0500 |
| commit | ea8cfdb5d19af45f98abe02844c7963dafec6e92 (patch) | |
| tree | 4a6054bf154d51588468f0344cf72e2ac9c49068 | |
| parent | 4695a2c50076879000ddde9f80d07bbcacfa0f26 (diff) | |
| download | qemu-ea8cfdb5d19af45f98abe02844c7963dafec6e92.zip qemu-ea8cfdb5d19af45f98abe02844c7963dafec6e92.tar.gz qemu-ea8cfdb5d19af45f98abe02844c7963dafec6e92.tar.bz2 | |
pcie: Add link speed and width fields to PCIESlot
Add fields allowing the PCIe link speed and width of a PCIESlot to
be configured, with an instance_post_init callback on the root port
parent class to set defaults. This allows child classes to set these
via properties or via their own instance_init callback, without
requiring all implementions to support arbitrary user selected values.
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/pci-bridge/pcie_root_port.c | 14 | ||||
| -rw-r--r-- | include/hw/pci/pcie_port.h | 4 |
2 files changed, 18 insertions, 0 deletions
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8c..34ad767 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -140,6 +140,19 @@ static Property rp_props[] = { DEFINE_PROP_END_OF_LIST() }; +static void rp_instance_post_init(Object *obj) +{ + PCIESlot *s = PCIE_SLOT(obj); + + if (!s->speed) { + s->speed = QEMU_PCI_EXP_LNK_2_5GT; + } + + if (!s->width) { + s->width = QEMU_PCI_EXP_LNK_X1; + } +} + static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *data) static const TypeInfo rp_info = { .name = TYPE_PCIE_ROOT_PORT, .parent = TYPE_PCIE_SLOT, + .instance_post_init = rp_instance_post_init, .class_init = rp_class_init, .abstract = true, .class_size = sizeof(PCIERootPortClass), diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0736014..df242a0 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -49,6 +49,10 @@ struct PCIESlot { /* pci express switch port with slot */ uint8_t chassis; uint16_t slot; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + QLIST_ENTRY(PCIESlot) next; }; |