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| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2023-09-11 14:32:23 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-09-21 10:39:51 +0200 |
| commit | e8eed838ec93314c164bf3416d80c9c893a2e8ee (patch) | |
| tree | 8cf65c8f01016cd1de05cd83ad78a07badf64288 | |
| parent | 3a2a1f97ea349745094e789e6b0768dbd92d0dcd (diff) | |
| download | qemu-e8eed838ec93314c164bf3416d80c9c893a2e8ee.zip qemu-e8eed838ec93314c164bf3416d80c9c893a2e8ee.tar.gz qemu-e8eed838ec93314c164bf3416d80c9c893a2e8ee.tar.bz2 | |
qemu/timer: Add host ticks function for RISC-V
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230911063223.742-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | include/qemu/timer.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 9a91cb1..9a366e5 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -979,6 +979,28 @@ static inline int64_t cpu_get_host_ticks(void) return cur - ofs; } +#elif defined(__riscv) && __riscv_xlen == 32 +static inline int64_t cpu_get_host_ticks(void) +{ + uint32_t lo, hi, tmph; + do { + asm volatile("RDTIMEH %0\n\t" + "RDTIME %1\n\t" + "RDTIMEH %2" + : "=r"(hi), "=r"(lo), "=r"(tmph)); + } while (unlikely(tmph != hi)); + return lo | (uint64_t)hi << 32; +} + +#elif defined(__riscv) && __riscv_xlen > 32 +static inline int64_t cpu_get_host_ticks(void) +{ + int64_t val; + + asm volatile("RDTIME %0" : "=r"(val)); + return val; +} + #else /* The host CPU doesn't have an easily accessible cycle counter. Just return a monotonically increasing value. This will be |