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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:43 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 11:56:05 +0200 |
| commit | e8dcfe825a51c5e963813343ec4112f06a0acf68 (patch) | |
| tree | 0f994f028ab03fec755e1b4f2f231485272e7834 | |
| parent | 706ce142056b1304ea21db53b73d128295771a71 (diff) | |
| download | qemu-e8dcfe825a51c5e963813343ec4112f06a0acf68.zip qemu-e8dcfe825a51c5e963813343ec4112f06a0acf68.tar.gz qemu-e8dcfe825a51c5e963813343ec4112f06a0acf68.tar.bz2 | |
target/mips: Clean up handling of CP0 register 18
Clean up handling of CP0 register 18.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
| -rw-r--r-- | target/mips/cpu.h | 20 | ||||
| -rw-r--r-- | target/mips/translate.c | 64 |
2 files changed, 44 insertions, 40 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d6405ad..d6ea111 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t; * Register 16 Register 17 Register 18 Register 19 * ----------- ----------- ----------- ----------- * - * 0 Config LLAddr WatchLo WatchHi - * 1 Config1 MAAR WatchLo WatchHi - * 2 Config2 MAARI WatchLo WatchHi - * 3 Config3 WatchLo WatchHi - * 4 Config4 WatchLo WatchHi - * 5 Config5 WatchLo WatchHi - * 6 WatchLo WatchHi - * 7 WatchLo WatchHi + * 0 Config LLAddr WatchLo0 WatchHi + * 1 Config1 MAAR WatchLo1 WatchHi + * 2 Config2 MAARI WatchLo2 WatchHi + * 3 Config3 WatchLo3 WatchHi + * 4 Config4 WatchLo4 WatchHi + * 5 Config5 WatchLo5 WatchHi + * 6 WatchLo6 WatchHi + * 7 WatchLo7 WatchHi * * * Register 20 Register 21 Register 22 Register 23 @@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG18__WATCHLO1 1 #define CP0_REG18__WATCHLO2 2 #define CP0_REG18__WATCHLO3 3 +#define CP0_REG18__WATCHLO4 4 +#define CP0_REG18__WATCHLO5 5 +#define CP0_REG18__WATCHLO6 6 +#define CP0_REG18__WATCHLO7 7 /* CP0 Register 19 */ #define CP0_REG19__WATCHHI0 0 #define CP0_REG19__WATCHHI1 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index edeaaad..6a11e8d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchlo, arg, sel); register_name = "WatchLo"; @@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); register_name = "WatchLo"; @@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchlo, arg, sel); register_name = "WatchLo"; @@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); register_name = "WatchLo"; |