diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-03 17:55:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-03 17:55:03 +0100 |
| commit | e7e5a9595ab1136845c444141830fca0d2746a73 (patch) | |
| tree | 590db25674096759f198b18bbbe8f1e52146d57e | |
| parent | 45a150aa2b3492acf6691c7bdbeb25a8545d8345 (diff) | |
| download | qemu-e7e5a9595ab1136845c444141830fca0d2746a73.zip qemu-e7e5a9595ab1136845c444141830fca0d2746a73.tar.gz qemu-e7e5a9595ab1136845c444141830fca0d2746a73.tar.bz2 | |
hw/arm/netduino2, netduinoplus2: Set system_clock_scale
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
global, which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.
Set the global to match the documented CPU clock speed of these boards.
Judging by the data sheet this is slightly simplistic because the
SoC allows configuration of the SYSCLK source and frequency via the
RCC (reset and clock control) module, but we don't model that.
Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
| -rw-r--r-- | hw/arm/netduino2.c | 10 | ||||
| -rw-r--r-- | hw/arm/netduinoplus2.c | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 79e1939..8f10334 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -30,10 +30,20 @@ #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" +/* Main SYSCLK frequency in Hz (120MHz) */ +#define SYSCLK_FRQ 120000000ULL + static void netduino2_init(MachineState *machine) { DeviceState *dev; + /* + * TODO: ideally we would model the SoC RCC and let it handle + * system_clock_scale, including its ability to define different + * possible SYSCLK sources. + */ + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; + dev = qdev_new(TYPE_STM32F205_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 958d21d..68abd3e 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -30,10 +30,20 @@ #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +/* Main SYSCLK frequency in Hz (168MHz) */ +#define SYSCLK_FRQ 168000000ULL + static void netduinoplus2_init(MachineState *machine) { DeviceState *dev; + /* + * TODO: ideally we would model the SoC RCC and let it handle + * system_clock_scale, including its ability to define different + * possible SYSCLK sources. + */ + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; + dev = qdev_new(TYPE_STM32F405_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |