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authorRabin Vincent <rabin@rab.in>2014-05-01 15:24:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-01 15:24:44 +0100
commite3da9921ebc554fad3224a9fdda9a7425ffd9ef7 (patch)
treeffbf06134096b9031f25cf43cc1102a867d2cad5
parent3b7715796401ad1b00f752217fe8f425915e801b (diff)
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armv7m_nvic: fix CPUID Base Register
cp15.c0_cpuid is never initialized for ARMv7-M; take the value directly from cpu->midr instead. Signed-off-by: Rabin Vincent <rabin@rab.in> Message-id: 1398036308-32166-1-git-send-email-rabin@rab.in Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/intc/armv7m_nvic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6066fa6..f5b0c3b 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -173,7 +173,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
return 10000;
case 0xd00: /* CPUID Base. */
cpu = ARM_CPU(current_cpu);
- return cpu->env.cp15.c0_cpuid;
+ return cpu->midr;
case 0xd04: /* Interrupt Control State. */
/* VECTACTIVE */
val = s->gic.running_irq[0];