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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:38 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 11:54:40 +0200 |
| commit | e3c7559d8902fbb9857fb94fc5391f258cc3c4d1 (patch) | |
| tree | 02e6c22a02d28887f05caa955326d042ea252026 | |
| parent | 2b0848674b4143bf5b2b6f7de6b8587dd52c31dd (diff) | |
| download | qemu-e3c7559d8902fbb9857fb94fc5391f258cc3c4d1.zip qemu-e3c7559d8902fbb9857fb94fc5391f258cc3c4d1.tar.gz qemu-e3c7559d8902fbb9857fb94fc5391f258cc3c4d1.tar.bz2 | |
target/mips: Clean up handling of CP0 register 13
Clean up handling of CP0 register 13.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-15-git-send-email-aleksandar.markovic@rt-rk.com>
| -rw-r--r-- | target/mips/cpu.h | 2 | ||||
| -rw-r--r-- | target/mips/translate.c | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 061effb..4fce05a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -357,6 +357,8 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG12__GTOFFSET 7 /* CP0 Register 13 */ #define CP0_REG13__CAUSE 0 +#define CP0_REG13__VIEW_RIPL 4 +#define CP0_REG13__NESTEDEXC 5 /* CP0 Register 14 */ #define CP0_REG14__EPC 0 /* CP0 Register 15 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index fb9c719..4da08e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7202,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_13: switch (sel) { - case 0: + case CP0_REG13__CAUSE: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); register_name = "Cause"; break; @@ -7928,7 +7928,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_13: switch (sel) { - case 0: + case CP0_REG13__CAUSE: save_cpu_state(ctx, 1); gen_helper_mtc0_cause(cpu_env, arg); /* @@ -8677,7 +8677,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_13: switch (sel) { - case 0: + case CP0_REG13__CAUSE: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); register_name = "Cause"; break; @@ -9391,7 +9391,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_13: switch (sel) { - case 0: + case CP0_REG13__CAUSE: save_cpu_state(ctx, 1); gen_helper_mtc0_cause(cpu_env, arg); /* |