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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-17 09:43:12 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-17 09:43:12 +0000 |
| commit | e35298cd1f00849477c65355db97e7400e1519dc (patch) | |
| tree | a3b4a27df774b673d383dd7659e52e191d372d4a | |
| parent | 9a7f32283ca284ae0a2482a20d21f0cc08ac6dbf (diff) | |
| download | qemu-e35298cd1f00849477c65355db97e7400e1519dc.zip qemu-e35298cd1f00849477c65355db97e7400e1519dc.tar.gz qemu-e35298cd1f00849477c65355db97e7400e1519dc.tar.bz2 | |
Generate better code for Sparc32 shifts
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4467 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-sparc/translate.c | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 5b1b291..f89d13e 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3008,18 +3008,33 @@ static void disas_sparc_insn(DisasContext * dc) break; #ifndef TARGET_SPARC64 case 0x25: /* sll */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; case 0x26: /* srl */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; case 0x27: /* sra */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; #endif |