diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-09-16 16:22:14 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | e1d635e871f4e0dcea7ec08309509bbb82c2047c (patch) | |
| tree | ebbbd7c9050a0e54f814f578163ad41842a940fb | |
| parent | c1f55d9795b69f17f002b7d6e8580bcd23f49be5 (diff) | |
| download | qemu-e1d635e871f4e0dcea7ec08309509bbb82c2047c.zip qemu-e1d635e871f4e0dcea7ec08309509bbb82c2047c.tar.gz qemu-e1d635e871f4e0dcea7ec08309509bbb82c2047c.tar.bz2 | |
target/hppa: Truncate rotate count in trans_shrpw_sar
When forcing rotate by i32, the shift count must be as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/hppa/translate.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 20e44ed..d6ccce0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3105,8 +3105,11 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (a->r1 == a->r2) { TCGv_i32 t32 = tcg_temp_new_i32(); + TCGv_i32 s32 = tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_rotr_i32(t32, t32, cpu_sar); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_rotr_i32(t32, t32, s32); tcg_gen_extu_i32_reg(dest, t32); } else { TCGv_i64 t = tcg_temp_new_i64(); |