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| author | Babu Moger <babu.moger@amd.com> | 2025-05-08 14:58:02 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-28 19:35:55 +0200 |
| commit | dfd5b456108a75588ab094358ba5754787146d3d (patch) | |
| tree | 5b2de8df029464b436272915169bfabc79ced745 | |
| parent | fc014d9ba5b26b27401e0e88a4e1ef827c68fe64 (diff) | |
| download | qemu-dfd5b456108a75588ab094358ba5754787146d3d.zip qemu-dfd5b456108a75588ab094358ba5754787146d3d.tar.gz qemu-dfd5b456108a75588ab094358ba5754787146d3d.tar.bz2 | |
target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX
Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
support for IC prefetch.
CPUID_Fn80000021_EAX
Bit Feature description
20 Indicates support for IC prefetch.
1 FsGsKernelGsBaseNonSerializing.
WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing.
Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/a5f6283a59579b09ac345b3f21ecb3b3b2d92451.1746734284.git.babu.moger@amd.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 4 | ||||
| -rw-r--r-- | target/i386/cpu.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d01a808..0d1b907 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1253,12 +1253,12 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_8000_0021_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, + "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, NULL, NULL, "null-sel-clr-base", NULL, "auto-ibrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "prefetchi", NULL, NULL, NULL, "eraps", NULL, NULL, "sbpb", "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 22e8244..1146465 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1092,12 +1092,16 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); /* Processor ignores nested data breakpoints */ #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) +/* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */ +#define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1) /* LFENCE is always serializing */ #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) /* Null Selector Clears Base */ #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) /* Automatic IBRS */ #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) +/* Indicates support for IC prefetch */ +#define CPUID_8000_0021_EAX_PREFETCHI (1U << 20) /* Enhanced Return Address Predictor Scurity */ #define CPUID_8000_0021_EAX_ERAPS (1U << 24) /* Selective Branch Predictor Barrier */ |