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authorMarcin Juszkiewicz <marcin.juszkiewicz@linaro.org>2024-05-26 13:45:51 -0700
committerPeter Maydell <peter.maydell@linaro.org>2024-05-30 15:45:21 +0100
commitdaf9748ac002ec35258e5986b6257961fd04b565 (patch)
tree49d0de848dd4ce7a9678af8bfad831e722df9269
parentfa31b7e1681cfe20917f172b537a3a0988efc583 (diff)
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target/arm: Disable SVE extensions when SVE is disabled
Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240526204551.553282-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu64.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c15d086..862d2b9 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -109,7 +109,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* No explicit bits enabled, and no implicit bits from sve-max-vq.
*/
if (!cpu_isar_feature(aa64_sve, cpu)) {
- /* SVE is disabled and so are all vector lengths. Good. */
+ /*
+ * SVE is disabled and so are all vector lengths. Good.
+ * Disable all SVE extensions as well.
+ */
+ cpu->isar.id_aa64zfr0 = 0;
return;
}