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authorLi Chen <chenl311@chinatelecom.cn>2025-05-28 18:53:37 +0800
committerMichael S. Tsirkin <mst@redhat.com>2025-07-14 09:16:40 -0400
commitda77fc6c2e28a17249a6f459213247720e22e170 (patch)
treed35cd652d6604e0300ff8de60dd1db68b1cbec6e
parent9ce87106c7bcb1c2ada17e578db87f13ac29ae92 (diff)
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tests/qtest/bios-tables-test: Add test for disabling SPCR on RISC-V
Add ACPI SPCR table test case for RISC-V when SPCR was off. Signed-off-by: Li Chen <chenl311@chinatelecom.cn> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Message-Id: <20250528105404.457729-4-me@linux.beauty> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-rw-r--r--tests/qtest/bios-tables-test.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c84cf10..e988dea 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1807,6 +1807,26 @@ static void test_acpi_aarch64_virt_tcg_acpi_spcr(void)
" -machine spcr=off", &data);
free_test_data(&data);
}
+
+static void test_acpi_riscv64_virt_tcg_acpi_spcr(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ .variant = ".acpispcr",
+ };
+
+ test_acpi_one("-cpu rva22s64 "
+ "-machine spcr=off", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_tcg_acpi_hmat(const char *machine, const char *arch)
{
test_data data = {};
@@ -2701,6 +2721,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
qtest_add_func("acpi/virt/numamem",
test_acpi_riscv64_virt_tcg_numamem);
+ qtest_add_func("acpi/virt/acpispcr",
+ test_acpi_riscv64_virt_tcg_acpi_spcr);
}
} else if (strcmp(arch, "loongarch64") == 0) {
if (has_tcg) {