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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-30 22:49:50 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-05 09:35:51 +0100 |
| commit | d95101d6026641e9116225b5a22bbe6c4621828d (patch) | |
| tree | 9b976ecb3277b53c2f998ade3682d52f8de85a04 | |
| parent | 39107337181e0cfcbd92e67d10dce3acd5a13f0a (diff) | |
| download | qemu-d95101d6026641e9116225b5a22bbe6c4621828d.zip qemu-d95101d6026641e9116225b5a22bbe6c4621828d.tar.gz qemu-d95101d6026641e9116225b5a22bbe6c4621828d.tar.bz2 | |
target/arm: Name CPState type
Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpregs.h | 6 | ||||
| -rw-r--r-- | target/arm/helper.c | 6 |
2 files changed, 7 insertions, 5 deletions
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 858c5da..4179a8c 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -114,11 +114,11 @@ enum { * Note that we rely on the values of these enums as we iterate through * the various states in some places. */ -enum { +typedef enum { ARM_CP_STATE_AA32 = 0, ARM_CP_STATE_AA64 = 1, ARM_CP_STATE_BOTH = 2, -}; +} CPState; /* * ARM CP register secure state flags. These flags identify security state @@ -260,7 +260,7 @@ struct ARMCPRegInfo { uint8_t opc1; uint8_t opc2; /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; + CPState state; /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ diff --git a/target/arm/helper.c b/target/arm/helper.c index a19e04b..d560a6a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) } static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, + void *opaque, CPState state, int secstate, int crm, int opc1, int opc2, const char *name) { @@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2, state; + int crm, opc1, opc2; int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; + CPState state; + /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); /* op0 only exists in the AArch64 encodings */ |