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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-10-05 05:21:43 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-10-13 11:27:05 -0700 |
| commit | d73d4a5d78cabc55c837bc3303326659d8bc23a0 (patch) | |
| tree | f13425577c2f2dbd6e76120759e51ba7d9ae70b4 | |
| parent | 32142b807726e56b422c6990454f5dca0ef8d80f (diff) | |
| download | qemu-d73d4a5d78cabc55c837bc3303326659d8bc23a0.zip qemu-d73d4a5d78cabc55c837bc3303326659d8bc23a0.tar.gz qemu-d73d4a5d78cabc55c837bc3303326659d8bc23a0.tar.bz2 | |
target/hppa: Fix priority of T, D, and B page faults
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/hppa/mem_helper.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f027c49..f71cedd 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -288,7 +288,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } /* - * In priority order, check for conditions which raise faults. + * In reverse priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, * so that the resulting PROT will force a re-check of the * architectural TLB entry for the next access. @@ -299,13 +299,15 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - } else if (!ent->d) { + } + if (unlikely(!ent->d)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* The D bit is not set -- TLB Dirty Bit Fault. */ ret = EXCP_TLB_DIRTY; } - } else if (unlikely(ent->b)) { + } + if (unlikely(ent->b)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* |