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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-09-27 09:05:33 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-10-15 12:21:06 -0300 |
| commit | d70e58958da3165bb35d33a69c9d1937674dd6ce (patch) | |
| tree | 79a95cad0eae35376cec4a623a422ee127c39093 | |
| parent | 35845cf8fe8b484dcd5cead7a2b68d7c3099948b (diff) | |
| download | qemu-d70e58958da3165bb35d33a69c9d1937674dd6ce.zip qemu-d70e58958da3165bb35d33a69c9d1937674dd6ce.tar.gz qemu-d70e58958da3165bb35d33a69c9d1937674dd6ce.tar.bz2 | |
target/mips: Expose MIPSCPU::is_big_endian property
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-15-philmd@linaro.org>
| -rw-r--r-- | target/mips/cpu.c | 12 | ||||
| -rw-r--r-- | target/mips/cpu.h | 3 |
2 files changed, 11 insertions, 4 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1..04bf4b1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,10 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; -#if TARGET_BIG_ENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); env->CP0_Config1 = env->cpu_model->CP0_Config1; env->CP0_Config2 = env->cpu_model->CP0_Config2; env->CP0_Config3 = env->cpu_model->CP0_Config3; @@ -541,6 +539,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = { }; #endif +static Property mips_cpu_properties[] = { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +574,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) DeviceClass *dc = DEVICE_CLASS(c); ResettableClass *rc = RESETTABLE_CLASS(c); + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a1..070e11f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; /** |