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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2023-10-04 09:37:57 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2023-10-06 10:33:43 +0200 |
| commit | d05cad2bf6daff56c46e7c42f56fe39bd7bcbc06 (patch) | |
| tree | 32cf363b88a5d80c74129a49dbf5f23d7b401b4d | |
| parent | 7afc4356c39ffff7cade349808618878a1dbcf1e (diff) | |
| download | qemu-d05cad2bf6daff56c46e7c42f56fe39bd7bcbc06.zip qemu-d05cad2bf6daff56c46e7c42f56fe39bd7bcbc06.tar.gz qemu-d05cad2bf6daff56c46e7c42f56fe39bd7bcbc06.tar.bz2 | |
swim: add trace events for IWM and ISM registers
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20231004083806.757242-12-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| -rw-r--r-- | hw/block/swim.c | 14 | ||||
| -rw-r--r-- | hw/block/trace-events | 7 |
2 files changed, 21 insertions, 0 deletions
diff --git a/hw/block/swim.c b/hw/block/swim.c index 333da08..7df36ea 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -19,6 +19,7 @@ #include "hw/block/block.h" #include "hw/block/swim.h" #include "hw/qdev-properties.h" +#include "trace.h" /* IWM registers */ @@ -125,6 +126,13 @@ #define SWIM_HEDSEL 0x20 #define SWIM_MOTON 0x80 +static const char *swim_reg_names[] = { + "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER", + "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1", + "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER", + "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE" +}; + static void fd_recalibrate(FDrive *drive) { } @@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; swimctrl->regs[reg >> 1] = reg & 1; + trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1)); if (swimctrl->regs[IWM_Q6] && swimctrl->regs[IWM_Q7]) { @@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, if (value == 0x57) { swimctrl->mode = SWIM_MODE_SWIM; swimctrl->iwm_switch = 0; + trace_swim_iwm_switch(); } break; } @@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) swimctrl->regs[reg >> 1] = reg & 1; + trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1)); return 0; } @@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; + trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value); + switch (reg) { case SWIM_WRITE_PHASE: swimctrl->swim_phase = value; @@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) break; } + trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value); return value; } diff --git a/hw/block/trace-events b/hw/block/trace-events index 34be8b9..c041ec4 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0 m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8 m25p80_binding(void *s) "[%p] Binding to IF_MTD drive" m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM" + +# swim.c +swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 +swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 +swim_iwm_switch(void) "switch from IWM to SWIM mode" |