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| author | Nicholas Piggin <npiggin@gmail.com> | 2025-05-12 13:10:43 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-21 08:03:53 +0200 |
| commit | cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf (patch) | |
| tree | 81fd50779ff93e1f59b3cb27f6dd2657b30d3706 | |
| parent | 581bec5a04c5c27a86cfae93ca531c101f2df2ec (diff) | |
| download | qemu-cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf.zip qemu-cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf.tar.gz qemu-cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf.tar.bz2 | |
ppc/xive: tctx_accept only lower irq line if an interrupt was presented
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-35-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
| -rw-r--r-- | hw/intc/xive.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 119a178..db26dae 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); - qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); - if (xive_nsr_indicates_exception(sig_ring, nsr)) { uint8_t cppr = sig_regs[TM_PIPR]; uint8_t ring; @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) /* Clear the exception from NSR */ sig_regs[TM_NSR] = 0; + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); trace_xive_tctx_accept(tctx->cs->cpu_index, ring, regs[TM_IPB], sig_regs[TM_PIPR], |