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| author | Luc Michel <luc.michel@amd.com> | 2023-10-17 21:44:19 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-10-27 15:27:06 +0100 |
| commit | ce077875da2493787985d4a747bacc924b279081 (patch) | |
| tree | cd32a1c2f0d51e1282140215f8320c5c3f1642f0 | |
| parent | 987e80601724207ffb747d6a12d718d3829b9c7b (diff) | |
| download | qemu-ce077875da2493787985d4a747bacc924b279081.zip qemu-ce077875da2493787985d4a747bacc924b279081.tar.gz qemu-ce077875da2493787985d4a747bacc924b279081.tar.bz2 | |
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/net/cadence_gem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 7e6cab7..dffcc64 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -283,7 +283,7 @@ REG32(DESCONF3, 0x288) REG32(DESCONF4, 0x28c) REG32(DESCONF5, 0x290) REG32(DESCONF6, 0x294) -#define GEM_DESCONF6_64B_MASK (1U << 23) + FIELD(DESCONF6, DMA_ADDR_64B, 23, 1) REG32(DESCONF7, 0x298) REG32(INT_Q1_STATUS, 0x400) @@ -1463,7 +1463,7 @@ static void gem_reset(DeviceState *d) s->regs[R_DESCONF] = 0x02D00111; s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; s->regs[R_DESCONF5] = 0x002f2045; - s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; + s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK; s->regs[R_INT_Q1_MASK] = 0x00000CE6; s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; |