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| author | Bibo Mao <maobibo@loongson.cn> | 2025-07-30 09:47:55 +0800 |
|---|---|---|
| committer | Bibo Mao <maobibo@loongson.cn> | 2025-08-29 10:05:02 +0800 |
| commit | cc78259deb21940521a227619eb00a4b8e3e36c2 (patch) | |
| tree | 4c8447bf1c8c966f767ef6fb894a8018c53735ae | |
| parent | f95b9702750507665f90e377b5c6c68274104024 (diff) | |
| download | qemu-cc78259deb21940521a227619eb00a4b8e3e36c2.zip qemu-cc78259deb21940521a227619eb00a4b8e3e36c2.tar.gz qemu-cc78259deb21940521a227619eb00a4b8e3e36c2.tar.bz2 | |
target/loongarch: Use correct address when flush tlb
With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit.
However on LoongArch TLB emulation system, virtual address is
48 bit. It is necessary to signed-extend 48 bit address to 64 bit when
flush tlb, also fix address calculation issue with odd page.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/loongarch/tcg/tlb_helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 7d3f986..9365860 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -115,16 +115,16 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index) tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); pagesize = MAKE_64BIT_MASK(tlb_ps, 1); mask = MAKE_64BIT_MASK(0, tlb_ps + 1); + addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; + addr = sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS); if (tlb_v0) { - addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */ tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, mmu_idx, TARGET_LONG_BITS); } if (tlb_v1) { - addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd */ - tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, + tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize, mmu_idx, TARGET_LONG_BITS); } } |