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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-05-15 16:09:41 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-05-25 23:39:11 +0200 |
| commit | c6c5fc5ab04533a22be11f377aa67d46e47056bf (patch) | |
| tree | 0ecc3c733dbd4e94f5142f362e65b27cb8bbc762 | |
| parent | b9ccbe212e2443294dd636cb17b4e436db8774a7 (diff) | |
| download | qemu-c6c5fc5ab04533a22be11f377aa67d46e47056bf.zip qemu-c6c5fc5ab04533a22be11f377aa67d46e47056bf.tar.gz qemu-c6c5fc5ab04533a22be11f377aa67d46e47056bf.tar.bz2 | |
hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Introduces the "hash_get_source_addr()" helper function to extract the source hash
buffer address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
| -rw-r--r-- | hw/misc/aspeed_hace.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 33e1397..b3c3af5 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -142,21 +142,30 @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov, return false; } +static uint64_t hash_get_source_addr(AspeedHACEState *s) +{ + uint64_t src_addr = 0; + + src_addr = deposit64(src_addr, 0, 32, s->regs[R_HASH_SRC]); + + return src_addr; +} + static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov) { - uint32_t src; + uint64_t src; void *haddr; hwaddr plen; int iov_idx; plen = s->regs[R_HASH_SRC_LEN]; - src = s->regs[R_HASH_SRC]; + src = hash_get_source_addr(s); haddr = address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr == NULL) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: Unable to map address, addr=0x%x, " - "plen=0x%" HWADDR_PRIx "\n", + "%s: Unable to map address, addr=0x%" HWADDR_PRIx + " ,plen=0x%" HWADDR_PRIx "\n", __func__, src, plen); return -1; } @@ -175,11 +184,12 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov, uint32_t pad_offset; uint32_t len = 0; uint32_t sg_addr; - uint32_t src; + uint64_t src; int iov_idx; hwaddr plen; void *haddr; + src = hash_get_source_addr(s); for (iov_idx = 0; !(len & SG_LIST_LEN_LAST); iov_idx++) { if (iov_idx == ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, @@ -188,8 +198,6 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov, return -1; } - src = s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE); - len = address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE, @@ -208,6 +216,8 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov, return -1; } + src += SG_LIST_ENTRY_SIZE; + iov[iov_idx].iov_base = haddr; if (acc_mode) { s->total_req_len += plen; |