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| author | Peter Maydell <peter.maydell@linaro.org> | 2025-08-19 15:56:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-08-30 16:37:23 +0100 |
| commit | c2fae597099ef6ff81ca63d69ee28eddb982d894 (patch) | |
| tree | 888a0048d2b790704db53f924cbe6a04607634ba | |
| parent | e0ca100425853aa362acefeb027800d952fb222d (diff) | |
| download | qemu-c2fae597099ef6ff81ca63d69ee28eddb982d894.zip qemu-c2fae597099ef6ff81ca63d69ee28eddb982d894.tar.gz qemu-c2fae597099ef6ff81ca63d69ee28eddb982d894.tar.bz2 | |
target/arm: Correct condition of aa64_atomics feature function
The ARMv8.1-Atomics feature (renamed FEAT_LSE in more modern versions
of the Arm ARM) has always ben indicated by ID_AA64ISAR0.ATOMIC being
0b0010 or greater; 0b0001 is a reserved unused value.
We were incorrectly checking for != 0; this had no harmful effects
because all the CPUs set their value for this field to either 0
(for not having the feature) or 2 (if they do have it), but it's
better to match what the architecture specifies here.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250819145659.2165160-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu-features.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 41511d0..d48754b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -408,7 +408,7 @@ static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2; } static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) |