diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2025-02-12 13:54:18 -0800 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2025-05-28 08:08:47 +0100 |
commit | bd07403fc146a9bfc5312404a63f24cc48701c97 (patch) | |
tree | 13028753d634977e0d87ac0dc4f734b862974375 | |
parent | b52ee0c1a4205c8d698c37557401d2f55e071fba (diff) | |
download | qemu-bd07403fc146a9bfc5312404a63f24cc48701c97.zip qemu-bd07403fc146a9bfc5312404a63f24cc48701c97.tar.gz qemu-bd07403fc146a9bfc5312404a63f24cc48701c97.tar.bz2 |
target/microblaze: Drop DisasContext.r0
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r-- | target/microblaze/translate.c | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index dc597b3..047d97e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -63,9 +63,6 @@ typedef struct DisasContext { DisasContextBase base; const MicroBlazeCPUConfig *cfg; - TCGv_i32 r0; - bool r0_set; - /* Decoder. */ uint32_t ext_imm; unsigned int tb_flags; @@ -179,14 +176,7 @@ static TCGv_i32 reg_for_read(DisasContext *dc, int reg) if (likely(reg != 0)) { return cpu_R[reg]; } - if (!dc->r0_set) { - if (dc->r0 == NULL) { - dc->r0 = tcg_temp_new_i32(); - } - tcg_gen_movi_i32(dc->r0, 0); - dc->r0_set = true; - } - return dc->r0; + return tcg_constant_i32(0); } static TCGv_i32 reg_for_write(DisasContext *dc, int reg) @@ -194,10 +184,7 @@ static TCGv_i32 reg_for_write(DisasContext *dc, int reg) if (likely(reg != 0)) { return cpu_R[reg]; } - if (dc->r0 == NULL) { - dc->r0 = tcg_temp_new_i32(); - } - return dc->r0; + return tcg_temp_new_i32(); } static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, @@ -1635,8 +1622,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cfg = &cpu->cfg; dc->tb_flags = dc->base.tb->flags; dc->ext_imm = dc->base.tb->cs_base; - dc->r0 = NULL; - dc->r0_set = false; dc->mem_index = cpu_mmu_index(cs, false); dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; dc->jmp_dest = -1; @@ -1675,11 +1660,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) trap_illegal(dc, true); } - if (dc->r0) { - dc->r0 = NULL; - dc->r0_set = false; - } - /* Discard the imm global when its contents cannot be used. */ if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); |