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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-08-22 18:28:47 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-08-24 11:22:42 -0700 |
| commit | bb9d7ee83e7279d71dae5dfba4d149abbf2c3b59 (patch) | |
| tree | 311ea7e3b43656d90895fc6bbeac9c9b364c6065 | |
| parent | 73f97f0aa34c1da9946b399ae92e7b65c51627b1 (diff) | |
| download | qemu-bb9d7ee83e7279d71dae5dfba4d149abbf2c3b59.zip qemu-bb9d7ee83e7279d71dae5dfba4d149abbf2c3b59.tar.gz qemu-bb9d7ee83e7279d71dae5dfba4d149abbf2c3b59.tar.bz2 | |
docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()
Commit 609ad70562 ("tcg: Split trunc_shr_i32 opcode into
extr[lh]_i64_i32") remove trunc_shr_i64_i32(). Update the
backend documentation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230822162847.71206-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | docs/devel/tcg-ops.rst | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 6a166c5..53695e1 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -882,14 +882,15 @@ sub2_i32, brcond2_i32). On a 64 bit target, the values are transferred between 32 and 64-bit registers using the following ops: -- trunc_shr_i64_i32 +- extrl_i64_i32 +- extrh_i64_i32 - ext_i32_i64 - extu_i32_i64 They ensure that the values are correctly truncated or extended when moved from a 32-bit to a 64-bit register or vice-versa. Note that the -trunc_shr_i64_i32 is an optional op. It is not necessary to implement -it if all the following conditions are met: +extrl_i64_i32 and extrh_i64_i32 are optional ops. It is not necessary +to implement them if all the following conditions are met: - 64-bit registers can hold 32-bit values - 32-bit values in a 64-bit register do not need to stay zero or |