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| author | Clément Léger <cleger@rivosinc.com> | 2024-04-22 15:58:36 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-03 11:12:11 +1000 |
| commit | ba7a1c52975a4068573deea4471535567393c366 (patch) | |
| tree | b7aeeff13cafd40881f78f4d6769414e7de62212 | |
| parent | 039003995047b2f7911142c7c5cfb845fda044fd (diff) | |
| download | qemu-ba7a1c52975a4068573deea4471535567393c366.zip qemu-ba7a1c52975a4068573deea4471535567393c366.tar.gz qemu-ba7a1c52975a4068573deea4471535567393c366.tar.bz2 | |
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068e..74318a9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -670,11 +670,11 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ - RISCV_EXCP_SEMIHOST = 0x10, RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, + RISCV_EXCP_SEMIHOST = 0x3f, } RISCVException; #define RISCV_EXCP_INT_FLAG 0x80000000 |