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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-05-17 10:57:07 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 16:56:12 +1000 |
| commit | b9a2b98e172336e8ec464b3b63bf0dedba944502 (patch) | |
| tree | 9452fd52a2e6c945265be382e7ed6da8bbd19e4a | |
| parent | 8c6eeb508a98b185fac71c4dad523763ab779a83 (diff) | |
| download | qemu-b9a2b98e172336e8ec464b3b63bf0dedba944502.zip qemu-b9a2b98e172336e8ec464b3b63bf0dedba944502.tar.gz qemu-b9a2b98e172336e8ec464b3b63bf0dedba944502.tar.bz2 | |
target/riscv: add PRIV_VERSION_LATEST
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at once when a new priv version is
available.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 8 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 |
2 files changed, 6 insertions, 4 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9fc9d1c..a0c4acf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; } #if defined(TARGET_RISCV64) @@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -462,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -475,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e431..1542358 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -61,6 +61,8 @@ enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + + PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, }; #define VEXT_VERSION_1_00_0 0x00010000 |