diff options
| author | Max Chou <max.chou@sifive.com> | 2025-06-27 21:30:13 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | b5092b3db23391d6ee770123715b76b85169d977 (patch) | |
| tree | d62bcdbfa53e334b9804ad19387bb7b1a6409708 | |
| parent | 29abd3d112c380b8019a77ebad65f61addfb812d (diff) | |
| download | qemu-b5092b3db23391d6ee770123715b76b85169d977.zip qemu-b5092b3db23391d6ee770123715b76b85169d977.tar.gz qemu-b5092b3db23391d6ee770123715b76b85169d977.tar.bz2 | |
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
According to the V spec, the vector fault-only-first load instructions
may change the VL CSR.
So the ldff_trans TCG translation function should generate the
lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
make sure the vl_eq_vlmax TB flag is correct.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250627133013.443997-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 2b6077a..4cd030c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1361,6 +1361,12 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, fn(dest, mask, base, tcg_env, desc); finalize_rvv_inst(s); + + /* vector unit-stride fault-only-first load may modify vl CSR */ + gen_update_pc(s, s->cur_insn_len); + lookup_and_goto_ptr(s); + s->base.is_jmp = DISAS_NORETURN; + return true; } |