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| author | Roman Artemev <roman.artemev@syntacore.com> | 2024-12-11 07:40:04 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-12 14:28:38 -0600 |
| commit | b438362a142527b97b638b7f0f35ebe11911a8d5 (patch) | |
| tree | b4cf64f0abed9cdc4c59e114d871052946bf69e8 | |
| parent | 04e006ab36a8565b92d4e21dd346367fbade7d74 (diff) | |
| download | qemu-b438362a142527b97b638b7f0f35ebe11911a8d5.zip qemu-b438362a142527b97b638b7f0f35ebe11911a8d5.tar.gz qemu-b438362a142527b97b638b7f0f35ebe11911a8d5.tar.bz2 | |
tcg/riscv: Fix StoreStore barrier generation
On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f8331e4..96f9a7e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) insn |= 0x02100000; } if (a0 & TCG_MO_ST_ST) { - insn |= 0x02200000; + insn |= 0x01100000; } tcg_out32(s, insn); } |