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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:28 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:53 +0100 |
| commit | b13c91c04b15f5216de9df3878da7dc4c1395979 (patch) | |
| tree | 88f1ce9ef4a03051f13ff731147050ac9cab354a | |
| parent | ef696cfbae6290d448ca0b36f9e41e3e0ec3d50d (diff) | |
| download | qemu-b13c91c04b15f5216de9df3878da7dc4c1395979.zip qemu-b13c91c04b15f5216de9df3878da7dc4c1395979.tar.gz qemu-b13c91c04b15f5216de9df3878da7dc4c1395979.tar.bz2 | |
target/arm: Use field names for manipulating EL2 and EL3 modes
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01176b2..7995ff2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) */ unset_feature(env, ARM_FEATURE_EL3); - /* Disable the security extension feature bits in the processor feature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &= ~0xf0; - cpu->isar.id_aa64pfr0 &= ~0xf000; + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } if (!cpu->has_el2) { @@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &= ~0xf00; - cpu->isar.id_pfr1 &= ~0xf000; + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } #ifndef CONFIG_USER_ONLY |