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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-10-19 12:27:05 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
| commit | ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5 (patch) | |
| tree | 9c9d01343909a99e828c57b6c983834271901a0c | |
| parent | 4bf501dc0118a28699e28c01acb34e28ddeb0acc (diff) | |
| download | qemu-ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5.zip qemu-ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5.tar.gz qemu-ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5.tar.bz2 | |
target/riscv: pmp: Ignore writes when RW=01
As per the Priv spec: "The R, W, and X fields form a collective WARL
field for which the combinations with R=0 and W=1 are reserved."
However currently such writes are not ignored as ought to be. The
combinations with RW=01 are allowed only when the Smepmp extension
is enabled and mseccfg.MML is set.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065705.1431868-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/pmp.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4dfaa28..162e88a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -123,6 +123,11 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (locked) { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n"); } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) { + /* If !mseccfg.MML then ignore writes with encoding RW=01 */ + if ((val & PMP_WRITE) && !(val & PMP_READ) && + !MSECCFG_MML_ISSET(env)) { + val &= ~(PMP_WRITE | PMP_READ); + } env->pmp_state.pmp[pmp_index].cfg_reg = val; pmp_update_rule_addr(env, pmp_index); return true; |