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| author | Jiaxi Chen <jiaxi.chen@linux.intel.com> | 2023-03-03 14:59:08 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-04-28 12:50:34 +0200 |
| commit | a9ce107fd0f2017af84255a9cf6542fa3eb3e214 (patch) | |
| tree | 15c4ea1370718c3b324da092eda6e32e284b0487 | |
| parent | fb6bbafc0f19385fb257ee073ed13dcaf613f2f8 (diff) | |
| download | qemu-a9ce107fd0f2017af84255a9cf6542fa3eb3e214.zip qemu-a9ce107fd0f2017af84255a9cf6542fa3eb3e214.tar.gz qemu-a9ce107fd0f2017af84255a9cf6542fa3eb3e214.tar.bz2 | |
target/i386: Add support for CMPCCXADD in CPUID enumeration
CMPccXADD is a new set of instructions in the latest Intel platform
Sierra Forest. This new instruction set includes a semaphore operation
that can compare and add the operands if condition is met, which can
improve database performance.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 7]
Add CPUID definition for CMPCCXADD.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-2-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 73dd993..67210ff 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -875,7 +875,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = CPUID_FEATURE_WORD, .feat_names = { NULL, NULL, NULL, NULL, - "avx-vnni", "avx512-bf16", NULL, NULL, + "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d243e29..d5843c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -907,6 +907,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* CMPCCXADD Instructions */ +#define CPUID_7_1_EAX_CMPCCXADD (1U << 7) /* Fast Zero REP MOVS */ #define CPUID_7_1_EAX_FZRM (1U << 10) /* Fast Short REP STOS */ |